The present invention relates to electronic circuits, and particularly to three dimensional electronic circuits that require vertical electrical interconnections between two or more layers in such circuits.
As high performance integrated circuit designs have been improved to provide greater speed of operation and to handle higher power levels, the technology for providing electrical interconnects in such circuits has become an increasingly significant issue. In operation, more powerful integrated circuits tend to use a greater proportion of their clock cycles to charge interconnect conductors, causing RC-induced delays and power consumption to become limiting factors for the performance of the circuit.
One approach to addressing this limitation is to move from two dimensional to three dimensional (3D) integration of a circuit's electronic components. In this approach, the components are fabricated on two or more separate wafers or dies, then integrated into a single chip-scale integrated circuit package.
3D integration allows the inclusion in a single integrated circuit of otherwise incompatible technologies, while providing significant advantages in performance, functionality, and form factor, as well as reduced size, weight, and power consumption. In addition, improved circuit performance results from reductions in inter-chip power, ground, and signal distribution line lengths, thereby significantly reducing signal propagation delays associated with chip-to-chip electrical signals.
Initial efforts toward 3D integration achieved inter-chip interconnects through wire bonding, bumped wafers, or connections over the edge of the die. Continued improvements in 3D integration led to through-wafer via interconnects, which provide electrical connections between various portions of the device circuitry by passing through the wafer, substrate, or other layers of the device. Multiple layers of routing metal, with the layers separated by dielectric material, are common elements of multilayer circuit processes, and these metal layers can be employed for horizontal (in-plane) signal routing.
A particular advantage of the through-wafer via approach to interconnects is the ability to employ die-level assembly. This permits selection of tested, known-good-die for 3D assembly. This also permits multiple layers of a three dimensional integrated circuit to be incorporated in a single photolithography reticle, processed at wafer level and diced into separate die, then stacked and bonded together in subsequent assembly processing.
The more traditional wafer-level assembly process, by contrast, requires a separate wafer for each layer of the integrated circuit, leading to the expense of a separate process run for each wafer. The net yield of the 3D stack may be low for advanced circuit processes as a result of low individual die yields. Further, by combining all of the integrated circuit layers in a single mask, processing the layers in a single wafer run, then dicing and stacking the layers as individual die, the fabrication cost for developing prototypes of the circuit can be significantly reduced.
One application, for example, that exploits the benefits of 3D integration using via interconnects is electronic imaging arrays. The integration of sensor arrays with 3D stacked layers of readout and signal processing circuitry can enable the implementation of massively parallel, densely interconnected imaging focal plane architectures, resulting in high resolution, high fill factor pixels, ultra-wide dynamic range, multispectral capability, and very fast imaging performance.
The implementation of a through-wafer via in a wafer requires that an exclusion zone be designed into the wafer at the point where the via will be located in each layer of the 3D integrated circuit. This exclusion zone must be free of circuit elements, such as transistors, and routing metals. Unfortunately, however, the nonuniformity of metal coverage caused by the presence of such exclusion zones can lead to the development of significant local topology, known as dishing, in the wafer during processing.
The severity of this dishing effect can be appreciated by considering the structure of a typical multilayer CMOS wafer, which may contain, for example, seven layers of routing metal, with dielectric layers on either side of each of the metal layers. In regions where there is no metal in one of the metal layers, a dishing effect will occur due to incomplete planarization. In regions where there is no metal in any of the metal layers, i.e., the exclusion zones, the dishing effect is compounded. In addition, if the distribution of metal density is non uniform across the wafer (for example, some regions have a high density of vias and hence many exclusion zones, while other regions have no vias and thus a relatively high density of metal) large changes in topology occur across the die area. This variation can cause a severe defocus during photolithographic processing, since all of the regions cannot be in focus simultaneously. The defocusing impairs or eliminates the ability to pattern fine features on the wafer. If the only effect was dishing at the via locations, the problem would be less serious, since there is no circuitry at those locations. Since the dishing phenomenon affects the ability to pattern the entire circuit, however, due to the topology introduced, the problem can become severe.
The dishing problem is exacerbated because the exclusion zones/absent metal layers are necessarily aligned vertically in all levels, at the location of each through-wafer via. Such dishing can detract from circuit functionality and yield, and is not limited to the via regions, but can affect the ability to properly pattern any portion of the circuit. The dishing effect is significant enough that it can prevent the ability to combine multiple independent die designs (layers) in a single reticle, thereby eliminating a key advantage of the through-wafer via interconnect.
Moreover, as processing advances to finer lines, the dishing effect becomes even more severe, since the depth of focus is reduced for smaller feature sizes and because a larger number of metal layers is typically involved in such advanced processing techniques.
For these reasons, a need has developed in the art for a through-wafer via interconnect which can be incorporated in 3D circuit design and processing while avoiding the negative effects of dishing.